v+ oe 1 2 3 5 top view a b gnd 4 sc-70 device marking: e4 DG2301 vishay siliconix new product document number: 72049 s-03420?rev. a, 03-mar-03 www.vishay.com 1 high-speed, low r on , spst analog switch (1-bit bus switch) features sc-70 5-lead package 5- switch connection between two ports minimal propagation delay through the switch low i cc zero bounce in flow-through mode control inputs compatible with ttl level description the DG2301 is a high-speed, 1-bit, low power, ttl-compatible bus switch. using sub-micron cmos technology, DG2301 achieves low on-resistance and negligible propagation delay. the DG2301 consist of a bi-directional input/output pins a and b. when the output enable (oe ) is low, the input/output pins are connected. when the oe is high, the switch is open and a high-impedance state exists between input/output pins a and b. functional block diagram and pin configuration truth table oe b function l a connect h hiz state disconnect ordering information temp range package part number -40 to 85 c sc70-5 DG2301dl
DG2301 vishay siliconix new product www.vishay.com 2 document number: 72049 s-03420?rev. a, 03-mar-03 absolute maximum ratings reference to gnd v+ -0.3 to +6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . oe , a, b a -0.3 to (v+ + 0.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous current (any terminal) 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . peak current 200 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (pulsed at 1 ms , 10% duty cycle) storage temperature (d suf fix) -65 to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . power dissipation (packages) b 6-pin sc70 c 250 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . notes: a. signals on a, or b or oe exceeding v+ will be clamped by internal diodes. limit forward diode current to maximum current ratings. b. all leads welded or soldered to pc board. c. derate 3.1 mw/ c above 70 c specifications (v+ = 5.0 v) test conditions otherwise unless specified limits - 40 to 85 c parameter symbol v+ = 4.0 v to 5.5 v, v oe = 0.8 or 2.0 v e temp a min b typ c max b unit dc characteristics v+ = 4.5 v, v a = 0 v, i b = 64 ma full 7 on resistance r on v+ = 4.5 v, v a = 0 v, i b = 30 ma full 7 on-resistance r on v+ = 4.5 v, v a = 2.4 v, i b = 15 ma full 15 v+ = 4.0 v, v a = 2.4 v, i b = 15 ma full 20 switch off leakage current i (off) v+ = 5.5 v, v a = 1 v/4.5 v, v b = 4.5 v/1 v full -10 10 a switchl-on leakage current i (on) v+ = 5.5 v, v a = v b = 1 v/4.5 v full -10 10 a input high voltage v ih full 2.0 v input low voltage v il full 0.8 v input current i il or i ih v oe = 0 or v+ full -1 1 a dynamic characteristics prop delay bus to bus f t phl v ld = open (figure 1 and 2) full 1 prop delay bus-to-bus f t plh v ld = open (figure 1 and 2) full 1 t pzl v ld = 7 v, v+ = 4.5 v to 5.5 v (figure 1 and 2) full 3.9 output enable time d t pzl v ld = 7 v, v+ = 4.0 v (figure 1 and 2) full 4.5 output enable time d t pzh v ld = open, v+ = 4.5 v to 5.5 v (figure 1 and 2) full 3.7 ns t pzh v ld = open, v+ = 4.0 v (figure 1 and 2) full 4.5 ns t plz v ld = 7 v, v+ = 4.5 v to 5.5 v (figure 1 and 2) full 4.0 output disable time d t plz v ld = 7 v, v+ = 4.0 v (figure 1 and 2) full 4.2 output disable time d t phz v ld = open, v+ = 4.5 v to 5.5 v (figure 1 and 2) full 1.0 t phz v ld = open, v+ = 4.0 v (figure 1 and 2) full 1.0 input capacitance c in room 3.5 channel-off capacitance d c (off) v oe = 0 or v+ f = 1 mhz room 5 pf channel-on capacitance d c on v oe = 0 or v+, f = 1 mhz room 11 p power supply power supply range v+ 4.0 5.5 v power supply current i+ v oe = 0 or v+ 0.01 1.0 a notes: a. room = 25 c, full = as determined by the operating suffix. b. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data s heet. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. guarantee by design, nor subjected to production test. e. v in = input voltage to perform proper function. f. guaranteed by design and not production tested. the bus switch propagation delay is a function of the rc time constant contr ibuted by the on-resistance and the specified load capacitance with an ideal voltage source (zero output impedance) driving the switch.
DG2301 vishay siliconix new product document number: 72049 s-03420?rev. a, 03-mar-03 www.vishay.com 3 ac loading and waveforms t r = 2.5 ns t f = 2.5 ns t f = 2.5 ns t r = 2.5 ns 3.0 v 3.0 v gnd gnd logic input switch input 10% 10% 10% 10% 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 90% 90% 90% 90% t w output output output t plh t phl v oh v ol t pzl t plz t pzh t phz 1.5 v v ol + 0.3 v v ol v oh v oh -0.3 v v ld 2 0 v oe logic input switch input ab v ld r a = 500 r b = 500 c l c l = 50 pf switch output input driven by 50- source terminated in 50 c l includes load and stray capacitance input prr = 1.0 mhz, t w = 50 ns figure 1. ac test circuit figure 2. ac waveforms
DG2301 vishay siliconix new product www.vishay.com 4 document number: 72049 s-03420?rev. a, 03-mar-03 typical characteristics (25 c unless noted) 0 20 40 60 80 100 120 012345 r on vs. v b single supply voltage v b - analog voltage (v) v+ = 4.5 v, i s = - 15 ma t = 25 c r on - on-resistance ( ) v+ = 4.5 v, i s = - 30 ma v+ = 4.5 v, i s = - 64 ma v+ = 4.0 v, i s = - 15 ma
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